CIS 451 Lab 2: Introduction to Sequential Circuits

Author: Greg Wolffe, modified by Zack Kurmas, further modified by Andrew Kalafut

Objective: The purpose of this lab is to provide a "hands-on" introduction to modern technologies for storing digital data. The lab will investigate basic storage device structure and function by building latches and experimenting with flip-flops. These simple devices will then be combined with combinational logic gates to construct sequential circuits. Voila! A state machine is born.

Deliverables: Submit in hardcopy a detailed lab report that includes your answers to the numbered questions.

This project should preferably be done in groups of 2. If there is sufficient equipment, you may work alone.


The equipment used will be much the same as the past few weeks - with the addition of a few more IC's. As always, please review and follow the guidelines presented for working with integrated circuits.

Simple Storage Devices

The first and simplest storage device we will consider is the S-R latch. It can be constructed using relatively simple logic; for example, the version presented in lecture used two NOR gates with feedback circuits. Figure 3-1 below gives the logic diagram.

NOR latch

Important: Note that the pinout of a NOR gate integrated circuit (74HC02) differs from the pinouts of the AND and NAND gate ICs used in previous labs. The figure below gives the pinout of a quad 2-input NOR gate IC.

NOR pinout

To investigate the operation of an S-R latch, construct the following circuit:

  1. Either (1) Demonstrate your circuit to the instructor, or (2) draw a labeled logic diagram of your circuit specifying your pin numbers. This diagram should look like Figure 3-1, with the input and output of each gate clearly labeled with the chip and pin number used.
  2. Notice that, unlike the combinatorial circuits we've built previously, the output of the S-R latch depends on both the inputs, and the current state of the device. A characteristic table is used to specify the output of the device in terms of both its input and current state. Determine, by observing the state of the LEDs, the characteristic table of the device.
    R S previous Q New Q New Q'
    0 0 0    
    0 0 1    
    0 1 0    
    0 1 1    
    1 0 0    
    1 0 1    
    1 1 0    
    1 1 1    
  3. What happens to Q and Q' when both inputs are set to logic 1?
  4. Explain how the circuit produces the observed result. (In other words write a couple paragraphs explaining why the output of this circuit makes sense given the defined behavior of its component gates when R=1 and S=1.)
  5. Describe a specific sequence of input values for R and S that could lead to Q being in an indeterminate (or random) state. (Hint: Consider what happens when R and S both change values "simultaneously".)


As described in class, the D flip-flop is a useful device for storing one bit of data. It does not suffer from the indeterminate state observed in the S-R latch. The logic device that will be used in this experiment is the 74HCT74, a dual D-type flip-flop with Set and Reset and a positive-edge trigger. The "dual" means there are two D flip-flops in the IC, the "Set and Reset" means that there are pins to Set and Reset the device, and "positive-edge trigger" indicates that a bit present on the D input will be latched into the flip-flop at the leading edge of a clock pulse.

The pinout of the D flip-flop is very different from the gates used previously. See Figure 3-3 below for the details of the pinout. Power is connected across pins 7 and 14 as usual. For flip-flop #1, pin 2 is the D (Data) input. The outputs Q and Q' are at pins 5 and 6 respectively. The Clock signal (CLK) is input to pin 3. Finally, pin 1 (labeled CLR) provides the Clear, or Reset function. Pin 4 (labeled PR) provides the Pre-set, or Set function. Both the Set and Clear inputs are active-LOW, which means they are in effect whenever a logic 0 is applied. In other words, connecting Set to ground will instantly set the state of the flip-flop to 1. No clock pulse is necessary to use set and reset. This entire organization is repeated, using different pins, for flip-flop #2.

D-latch pinout

Construct the following circuit:

Show the operation of the D flip-flop by completing the timing diagrams below: (Note: The diagrams below contain 8 vertical dotted lines. If you see fewer than 8 such lines, your web browser truncated the diagram.)

  1. This first diagram shows a typical clocked usage of the flip flop. When completing this diagram, assume PR and CLR (not shown) are always 1.

    Diagram 1

  2. This diagram shows typical preset / clear behavior. Note that the clock remains at 0 for the first half of the diagram.

    Diagram 2

  3. This diagram shows what happens when preset and clear are both low at the same time. The results of setting preset and clear to low at the same time are not defined, so the behavior may not be consistent.

    Diagram 3

Creating a Sequential Circuit

This last experiment provides a good example of the way storage devices and logic gates are used together to create a sequential circuit. It uses a combination of feedback (the current state of a storage device) together with combinational logic to create a device implementing a useful function.

  1. Report your observations using a characteristic table.
  2. Based on your observations, what useful circuit have you constructed? Hint: Make sure your LED for A1 is to the left of the LED for A0.
  3. Either (1) demonstrate your circuit to the instructor, or (2) draw a labeled logic diagram of your circuit specifying pin numbers. (Your diagram need not show the preset and clear inputs.)
circuit to build